Semiconductor Integration Materials Laboratory
SIM Lab
Semiconductor Integration Materials Laboratory
SIM Lab
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Yeonwoong Jung*
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Thickness Independent Semiconducting-to-Metallic Conversion in Wafer-Scale Two-Dimensional PtSe2 Layers by Plasma-Driven Chalcogen Defects Engineering
Horizontal-to-Vertical Transition of 2D Layer Orientation in Low-Temperature CVD-Grown PtSe2 and Its Influences on Electrical Properties and Device Applications
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